This invention relates to a non-volatile memory device with configurable row redundancy.
The invention relates, particularly but not exclusively, to semiconductor non-volatile memory devices which are electrically programmable and fabricated with CMOS technology, and the following description is made with reference to this field of application for convenience of explanation only.
As it is well known, a semiconductor non-volatile memory device of the so-called xe2x80x9cmultimegabitxe2x80x9d type, such as EEPROMs or Flash EPROMs, basically comprises a matrix of memory cells which accounts for a good proportion of the device area, specifically 40 to 70% of its total area.
The applications of such memory devices impose perfect performance of all the memory cells in the matrix during the device operation phases (reading, programming, erasing). In principle, the presence of at least one inoperative memory cell, commonly defined as xe2x80x9cbit-failxe2x80x9d, is sufficient to put the whole device out of use.
This requisite for utmost reliability of the memory device taxes the manufacture of this type of integrated device, because a generic memory cell in a batch has a not null probability of turning up defective. In particular, the main causes of bit-fails are connected to the technological process used to fabricate the integrated device, e.g., conductive layers shorted together, variations in the process parameters, breakdown of dielectric layers, and so on.
Lacking arrangements to detect and correct bit-fails, the percentage of devices with properly performing memory cells in a chosen fabricating batch would be low to qualify for mass production methods. This percentage shows the so called prime yield of the fabricating batch and plays a very important role in the whole manufacturing process.
In memory devices, this yield is actually dependent on the faultiness spread not only through the cell matrix interior, but also through ancillary circuits to such matrix. However, in consideration of the large area occupied by the memory, the reduced yield in devices of this type is mainly due to faults occurring within the matrix.
Suitable circuit arrangements for the detection and the correction of bit-fail are therefore employed to increase the yield in integrated memory devices.
According to a commonly used technique, spare memory cells are provided to replace those cells which have been found faulty in the matrix.
These spare memory cells, usually called redundant, are identical to the matrix memory cells they have to replace, and are suitably controlled by dedicated control circuits added to the standard device circuitry.
In particular, the memory layout prompts the use of entire redundant cell rows or columns, so that corresponding rows or columns of the memory matrix can be replaced even on the occurrence of only one bit-fail therein. In this way, a good compromise can be made between fault-correcting capability and the requested area to perform redundancy control circuits.
The choice of the type of layout of redundant cells for use in a memory device, e.g., row redundancy or column redundancy, or both, is essentially tied to the knowledge of the distribution and typology of the faults appearing in the matrix for a given technological integration process.
Moreover, the yield of a silicon integration process is not constant over time, since it is dependent on the actions performed to improve both the process characteristics and the circuit functional aspects. Typically, the yield is comparatively low at the start of the manufacturing process, to then improve as the production volume increases following to the process optimizing actions.
For example, with a well developed integration technology widely employed for mass production, the yield may attain its highest possible levels.
Of course, it is important to keep the manufacturing yield in memory devices high, possibly also from the very start of the manufacturing process.
In addition, every increase of the corrective capability of a redundancy architecture associated with a matrix of memory cells provokes an increase of the required area for its control circuitry, as well as an increase of the weight of the whole device complexity.
This added complexity becomes a serious problem with the row redundancy techniques, which heavily penalize, moreover, the access time to a memory word.
Thus, prior approaches provide optimal designed architectures for a given degree of the corrective capability, which degree is, therefore, fixed and unvaried for all the devices being manufactured.
In practice, implementing specific solutions with a high corrective capability involves an unacceptable longer time for accessing memory words, besides an increase in silicon area occupation, because of the complex control arrangements required.
One prior architecture aimed to reduced the access time of high corrective capability solutions making use of redundant rows is schematically shown in FIG. 1.
Particularly, the architecture 1 comprises a matrix 2, called matrix sector, of memory cells which are organized into regular rows and columns, a row decoder block 3, and a column decoder block 4, as well as a read block 5.
The read block 5 comprises basically read circuits (sense amplifiers) and output buffers.
The architecture 1 further comprises at least one matrix 6 of redundant cells, called redundancy sector, operative to correct bit-fails spread with equal probability over all the sectors of matrix 2.
The architecture 1 finally comprises a memory 7 of the UPROM (Unreasonable Programmable Read-Only Memory) type for row redundancy.
It should be considered that in a flash memory device, there are usually many sectors of memory cells having predetermined capacity. In fact the storage capacity of the sectors can be constant for all sectors or vary between sectors.
This organization in sectors allows each cell matrix to be accessed separately for read, program and erase operations. In particular, whereas a program operation is selective of byte/memory words for any memory sector, an erase operation is shared by all the cells of each selected sector.
Selective access to the sectors is, therefore, achieved by providing a row or a column type of organization of the sectors themselves and a physical separation of the source lines of each sector.
In particular, with a by-row organization, the columns are distributed among all the sectors, and the selection takes place by row address, whereas in a dual manner, with a by-column organization, the rows are distributed among all the sectors and the selection takes place by column address.
Furthermore, the by-row or by-column organization of the matrix sectors can be performed by using single or double silicon level technologies. With a by-row organization, rows shared by the sectors are realized in low-resistivity polysilicon, whereas the columns are realized in metal, while with a by-column organization, a second metal level can be used to lower the overall resistance of the polysilicon rows, superposing the metal layer in contact with the polysilicon rows.
In processes with at least two metal levels, the matrix sectors can be organized in a combined by-row and by-column way. In this case, the row (column) decoding can use a hierarchic organization based on xe2x80x9cglobalxe2x80x9d rows (columns), or rows shared by all the sectors to which the local rows (columns) of the individual sectors are connected. The local rows (columns) are particularly enabled only for a selected sector.
A hierarchic organization of this type (by the rows or the columns) has a major advantage in that the effects of electric noise on the shared lines between adjoining cells under the different operating conditions are reduced, since the local bit lines or local word lines are shared by the cells of the single sectors.
By using a technological process with at least three metal levels, hierarchic decoding at the same time of the row and of the column is made feasible. In fact, in such a process, the global rows are realized with a first metal level, while the local rows are realized by low-resistivity polysilicon; the global and local columns are instead realized with a second and a third metal level, respectively.
In a conventional architecture 1 as just described, faulty cells are spotted at the device EWS (Electrical Wafer Sorting) stage. In the presence of faulty cells, an associative memory 7, also shown schematically in FIG. 1, is controlled by on-chip control circuitry to allow a full matrix row xe2x80x9creplacementxe2x80x9d with a redundant row, in such a way that the access to the latter will be fully transparent to the ultimate user.
This replacement operation comprises storing the address of the faulty row permanently into non-volatile memory cells of the UPROM (Unerasable Programmable Read-Only Memory) type of the associative memory 7.
It should be specified that the term UPROM belongs to an EPROM technology wherein the UPROM cells are realized in a different manner from the memory cells, to avoid to erase them during exposure to UV radiation. On the other hand, with a flash technology, the erase operation is of the electrical type, and therefore the UPROM cells realized with such technology are actually identical to the memory cells. Nevertheless, it has become commonplace to use the term UPROM to indicate memory cells employed for storing redundant addresses, as well as in the instance of flash technology.
With the conventional architecture 1, the redundant lines can be pre-decoded by the same row decoding signals of the memory matrix sectors 2, thus achieving a compromise between the corrective capability of the redundancy employed and silicon area occupation.
The solution illustrated by FIG. 1 refers to flash technology implemented with a single or double metallization level technology, with hierarchic column decoding (hierarchic row decoding being non-limitative in application), with redundant cells provided in an associative memory, or rather in a redundant row sector 6, and with a shared source line.
In particular, the common source terminal of the redundant sector is associated with that of the sector which contains faulty cells. This condition is vital to the application because the architecture of a flash memory provides for the redundant cells to be erased simultaneously with those of their related sector.
The time for accessing a memory word in an architecture based on row redundancy is usually longer than that provided by architectures that do not employ such technique, due to the additional time required for redundancy handling (including comparing the row addresses, selecting a redundant row, etc.). This time is of about 10 ns for conventional memory devices and is inclusive of delay in the propagation of signals over interconnecting lines because of the less-than-ideal effects relating to their physical implementation.
Access time, moreover, is longer in a row redundancy architecture than in a column redundancy architecture, due to the different organization of the memory matrix in either cases.
In particular, in multimegabit flash memory devices exhibiting high parallelism during a burst read mode, the memory sectors are designed to include a significantly larger number of columns than of rows. Consequently, the row pre-charge time will be longer than the column time, mainly because of the increased RC load associated therewith.
For a given line load, pre-charge time is proportional to the final voltage sought; in case of reading with a higher gate voltage than the supply voltage Vdd (as in the case of multi-level memories or conventional two-level memories using a so-called gate-boosted reading technique), the penalty is heavier on access time because row pre-charging takes longer.
In order to minimize the effect on access time, the prior solution under consideration provides with a simultaneously pre-charging of both the selected and the redundant row, even where the former does not require to be replaced, at every change of address forced from outside. The evaluation of the redundant event for the selected row is carried out during the row pre-charging time, while the local columns are de-selected. In this way, uniformity of access time can be achieved for both devices provided with redundancy and devices which are not provided with redundancy.
In summary, this prior architecture does enhances the corrective capability of the whole device for only a predetermined number of redundant rows, by virtue of the matrix of memory cells having hierarchic decoding features, in particular of the redundant rows being organized within a dedicated sector with local column decoding.
This particular hierarchic decoding architecture provides, therefore, for optimum handling of row redundancy, maximizing corrective capability without penalty on memory word accessing time. In fact, with this architecture, some functional operations can be arranged to overlap in time, thus reducing the access time to the memory words. The architecture is, therefore, of special advantage with memory devices wherein the time required for pre-charging a selected row is longer than the time for sensing the redundancy event of such a row.
However, the prior solutions are advantageous at the initial stage of the manufacturing process, being justified by the need to obtain a high yield, and become gradually less useful, as the yield improves with the manufacturing process becoming more favorable over time.
An embodiment of this invention provides a memory architecture having row redundancy control, with such structural and functional features as to afford chip-by-chip re-configurability of the architecture corrective capability, thereby overcoming the drawbacks and limitations of prior art memory architectures.
Thus, the capability to recover faulty cells can be adjusted to fill actual demands during the fabrication of the architecture, achieving the best compromise between the corrective capability of the architecture and its effect on access time to the memory words of a cell matrix with which the architecture is associated.
A principle of this invention is one of configuring each device product at the EWS stage of its fabrication.
An embodiment of the invention is directed to a non-volatile memory device with configurable row redundancy, comprising:
a non-volatile memory, itself comprising at least one matrix of memory cells and at least one matrix of redundant memory cells, both organized into rows and columns;
row and column decoding circuits;
read and modify circuits for reading and modifying data stored in the memory cells; and
at least one associative memory matrix, also organized into rows and columns, able to store the addresses of faulty rows and related control circuits for controlling the associative memory matrix.
The features and advantages of the device according to the invention can be more clearly understood by reading the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.